The metal oxide semiconductor (MOSFET) transistor is one of the widely used devices in integrated circuits. The MOSFET device has a gate terminal, as well as source and drain terminals. The gate terminal is connected to the gate electrode, while the remaining terminals are connected to the heavily doped source and drain regions formed in the semiconductor substrate. A channel region in the semiconductor under the gate electrode separates the source and the drain.
FIG. 1 shows a schematic drawing of a layout of MOS transistors according to the prior art. A first region 10 is used to define the polysilicon gate of the MOS. The region 10 typically includes a plurality of first strip portions that are parallel to one another. A second strip portion is connected to those first strip portions and perpendicular to the first strip portions. A second region 12 is formed over the first region 10. The second region 12 is used for forming the impurity regions, i.e. the source and drain. The region 12 is divided into two major portions by the polysilicon gate. The first portions 12a of the second region 12 are utilized to form the source regions, while the remaining portions 12b are used to serve as the drain region. A third region 14 for forming contact holes is formed over the portions 12a of the second region 12. A fourth region 18 used to define a metal line is formed over the second region 12 and covers the third region 14. The contact region 14 can be used to create contact holes in an isolation layer, thereby providing an electrical path for connecting the source regions 12a via a metal line formed by using the fourth region 18. Similarly, the contact hole 16 can be also defined by the third region 14 or another region. The contact hole is used to provide an electrical path for connecting drains 12b.
The width of the polysilicon gate is denoted by "W" in FIG. 1. The junction between the polysilicon gate and the impurity region is denoted by "L". The ratio of W/L is preferably a higher number. In unit areas indicated by a-b-c-d, the ratio is 2W/L. However, the trends in the semiconductor industry is to fabricate integrated circuits that are scale down to an extremely compact dimensions and increase the packaging density of a wafer. Thus, it is desirable to layout a semiconductor device in a more compact dimension.